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2.5 msps, 24-bit, 100 db sigma-delta adc with on-chip buffer ad7760 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 120 db dynamic range at 78 khz output data rate 100 db dynamic range at 2.5 mhz output data rate 112 db snr at 78 khz output data rate 100 db snr at 2.5 mhz output data rate 2.5 mhz maximum fully filtered output word rate programmable oversampling rate (8 to 256) fully differential modulator input on-chip differential amplifier for signal buffering low-pass finite impulse response (fir) filter with default or user-programmable coefficients modulator output mode overrange alert bit digital offset and gain correction registers filter bypass modes low power and power-down modes synchronization of multiple devices via sync pin applications data acquisition systems vibration analysis instrumentation functional block diagram ad7760 v in + v in ? av dd 1 agnd mclk dgnd v drive av dd 2 av dd 3 av dd 4 dv dd decapa/b r bias db0 to db15 cs drdy rd/wr control logic i/o offset and gain registers diff multibit - modulator reconstruction v ref+ fir filter engine programmable decimation buf sync reset 0 4975-001 figure 1. general description the ad7760 is a high performance, 24-bit - analog-to-digital converter (adc). it combines wide input bandwidth and high speed with the benefits of - conversion to achieve a perfor- mance of 100 db snr at 2.5 msps, making it ideal for high speed data acquisition. wide dynamic range combined with significantly reduced antialiasing requirements simplify the design process. an integrated buffer to drive the reference, a differential amplifier for signal buffering and level shifting, an overrange flag, internal gain and offset registers, and a low-pass digital fir filter make the ad7760 a compact, highly integrated data acquisition device requiring minimal peripheral component selection. in addition, the device offers programmable decimation rates, and the digital fir filter can be adjusted if the default characteristics are not appropriate for the application. the ad7760 is ideal for applications demanding high snr without a complex front-end signal processing design. the differential input is sampled at up to 40 msps by an analog modulator. the modulator output is processed by a series of low- pass filters, with the final filter having default or user-programmable coefficients. the sample rate, filter corner frequencies, and output word rate are set by a combination of the external clock frequency and the configuration registers of the ad7760. the reference voltage supplied to the ad7760 determines the analog input range. with a 4 v reference, the analog input range is 3.2 v differential biased around a common mode of 2 v. this common-mode biasing can be achieved using the on-chip differential amplifier, further reducing the external signal conditioning requirements. the ad7760 is available in an exposed paddle, 64-lead tqfp and is specified over the industrial temperature range from ?40c to +85c. table 1. related devices part no. description ad7762 24-bit, 625 ksps, 109 db, - parallel interface ad7763 24-bit, 625 ksps, 109 db, - serial interface
important links for the ad7760 * last content update 07/14/2013 01:35 am parametric selection tables find similar products by operating parameters documentation ad7760 : tips & solutions to aid optimum performance an-311: how to reliably protect cmos circuits against power supply overvoltaging an-282: fundamentals of sampled data systems an-342: analog signal-handling for high speed and accuracy. an-280: mixed signal circuit technologies an-388: using sigma-delta converters-part 1 an-389: using sigma-delta converters-part 2 an-283: sigma-delta adcs and dacs ms-2210: designing power supplies for high speed adc two fast, two accurate a/d converters help eliminate front-end conditioning 18-bit sar, 20-bit delta-sigma adcs up the ante on converter specs new 18- and 24-bit adcs reduce design complexity, time, and cost suggested companion products recommended driver amplifiers for the ad7760 for low noise and low power applications, we recommend the ada4841-1 . for low power and 5v single supply, we suggest the ad8605, ad8615 or the ad8655 . for low noise, low power and low frequency, we recommend the op184 . for low noise and high frequency, try the ad8021 or the dual ad8022 . for low power, low frequency, small package, we recommend the ad8519 . for high frequency and low power, we suggest the ad8031 . recommended voltage reference for the ad7760 for high precision, ultralow noise and high output source and sink current, we recommend the adr431 (2.5v reference) or the adr434 (4.096v reference). recommended power solutions for selecting voltage regulator products, use adisimpower . for selecting supervisor products, use the supervisor parametric search . design tools, models, drivers & software sigma-delta adc tutorial evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ad7760 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ad7760 rev. a | page 2 of 36 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 3 specifications..................................................................................... 4 timing specifications .................................................................. 6 timing diagrams.......................................................................... 7 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 terminology .................................................................................... 11 typical performance characteristics ........................................... 12 theory of operation ...................................................................... 18 modulator data output mode...................................................... 19 modulator inputs........................................................................ 19 modulator data output scaling ............................................... 19 modulator data output mode interface ..................................... 20 clock divide-by-1 mode ( cdiv = 1) ..................................... 20 clock divide-by-2 mode ( cdiv = 0) ..................................... 20 using the ad7760 in modulator output mode..................... 21 ad7760 interface............................................................................ 22 reading data............................................................................... 22 reading status and other registers......................................... 22 sharing the parallel bus ............................................................. 22 synchronization.......................................................................... 22 writing to the ad7760 .............................................................. 23 clocking the ad7760 .................................................................... 24 buffering the mclk signal....................................................... 24 mclk jitter requirements ....................................................... 24 driving the ad7760....................................................................... 26 using the ad7760 ...................................................................... 27 decoupling and layout recommendations................................ 28 supply decoupling ..................................................................... 29 additional decoupling .............................................................. 29 reference voltage filtering ....................................................... 29 differential amplifier components ........................................ 29 bias resistor selection ............................................................... 29 layout considerations............................................................... 29 exposed paddle........................................................................... 29 programmable fir filter............................................................... 30 downloading a user-defined filter ............................................ 31 example filter download ......................................................... 31 ad7760 registers ........................................................................... 33 control register 1address 0x0001 ...................................... 33 control register 2address 0x0002 ...................................... 33 status register (read only) ...................................................... 34 offset registeraddress 0x0003............................................. 34 gain registeraddress 0x0004............................................... 34 overrange registeraddress 0x0005..................................... 34 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35
ad7760 rev. a | page 3 of 36 revision history 8/06rev. 0 to rev. a updated package option................................................... universal change to features............................................................................1 changes to specifications.................................................................4 changes to absolute maximum ratings........................................8 changes to terminology section ..................................................11 added figure 36 through figure 39 ............................................17 added modulator data output mode section ...........................19 added figure 41 through figure 47 ............................................19 added modulator data output mode interface section...........20 changes to reading data section.................................................22 added synchronizat ion section....................................................22 changes to clocking the ad7760 section...................................24 added buffering the mclk signal section.................................24 added mclk jitter requirements heading ...............................24 changes to driving the ad7760 section.....................................26 changes to figure 51 ......................................................................26 added figure 52 ..............................................................................26 changes to figure 55 ......................................................................28 changes to figure 56 ......................................................................29 added exposed paddle section.....................................................29 change to control register 2address 0x0002 section ..........33 changes to status register (read only) section ........................34 7/05revision 0: initial version
ad7760 rev. a | page 4 of 36 specifications av dd 1 = dv dd = v drive = 2.5 v, av dd 2 = av dd 3 = av dd 4 = 5 v, v ref+ = 4.096 v, mclk amplitude = 5 v, t a = 25c, normal mode, using the on-chip amplifier with components as shown in table 8 , unless otherwise noted. 1 table 2. parameter test conditions/comments specification unit dynamic performance decimate by 256 mclk = 40 mhz, odr = 78 khz, f in = 1 khz dynamic range modulator inputs shorted 119 db min 120.5 db typ signal-to-noise ratio (snr) 2 input amplitude = ?0.5 dbfs 112 db typ input amplitude = ?60 dbfs 59 db typ spurious-free dynamic range (sfdr) nonharmon ic, input amplitude = ?6 dbfs 126 dbc typ input amplitude = ?60 dbfs 77 dbc typ total harmonic distortion (thd) inp ut amplitude = ?0.5 dbfs ?105 db typ input amplitude = ?6 dbfs ?106 db typ input amplitude = ?60 dbfs ?75 db typ decimate by 32 mclk = 40 mhz, odr = 625 khz, f in =100 khz dynamic range modulator inputs shorted 108 db min 109.5 db typ signal-to-noise ratio (snr) 2 input amplitude = ?0.5 dbfs 107 db typ spurious-free dynamic range (sfdr) nonharmon ic, input amplitude = ?6 dbfs 120 dbc typ total harmonic distortion (thd) inp ut amplitude = ?0.5 dbfs ?105 db typ input amplitude = ?6 dbfs ?106 db typ decimate by 8 mclk = 40 mhz, odr = 2.5 mhz dynamic range modulator inputs shorted 99 db min 100.5 db typ signal-to-noise ratio (snr) 2 f in = 1 khz, input amplitude = ?0.5 dbfs 100 db typ f in = 100 khz, input amplitude = ?0.5 dbfs 99 db typ f in = 1 mhz, input amplitude = ?0.5 dbfs 98 db typ spurious-free dynamic range (sfdr) nonharmonic, f in = 100 khz, input amplitude = ?6 dbfs 120 dbc typ nonharmonic, f in = 1 mhz, input amplitude = ?6 dbfs 114 dbc typ total harmonic distortion (thd) input amplitude = ?0.5 dbfs, f in = 100 khz ?103 db typ input amplitude = ?6 dbfs, f in = 100 khz ?102 db typ imd second order f in a = 989.95 khz, f in b = 999.95 khz ?115 db typ imd third order f in a = 989.95 khz, f in b = 999.95 khz ?89 db typ dc accuracy resolution 24 bits differential nonlinearity guaranteed monotonic to 24 bits integral nonlinearity 0.00076 % typ zero error 0.014 % typ 0.02 % max gain error 0.016 % typ zero error drift 0.00001 % fs/c typ gain error drift 0.0002 % fs/c typ digital filter response decimate by 8 group delay mclk = 40 mhz 12 s typ decimate by 32 group delay mclk = 40 mhz 47 s typ decimate by 256 group delay mclk = 40 mhz 358 s typ
ad7760 rev. a | page 5 of 36 parameter test conditions/comments specification unit analog input differential input voltage v in (+) C v in (?), v ref = 2.5 v 2 v p-p v in (+) C v in (?), v ref = 4.096 v 3.25 v p-p input capacitance at internal buffer inputs 5 pf typ at modulator inputs 55 pf typ reference input/output v ref input voltage v dd 3 = 3.3 v 5% +2.5 v max v dd 3 = 5 v 5% +4.096 v max v ref input dc leakage current 6 a max v ref input capacitance 5 pf max power dissipation total power dissipation normal mode 958 mw max low power mode 661 mw max standby mode clock stopped 6.35 mw max power requirements av dd 1 (modulator supply) 5% +2.5 v av dd 2 (general supply) 5% +5 v av dd 3 (differential amplifier supply) +3.15/+5.25 v min/max av dd 4 (reference buffer supply) +3.15/+5.25 v min/max dv dd 5% +2.5 v v drive +1.65/+2.7 v min/max normal mode ai dd 1 (modulator) 49/51 ma typ/max ai dd 2 (general) 3 40/42 ma typ/max ai dd 4 (reference buffer) av dd 4 = 5 v 34/36 ma typ/max low power mode ai dd 1 (modulator) 26/28 ma typ/max ai dd 2 (general) 3 20/23 ma typ/max ai dd 4 (reference buffer) av dd 4 = 5 v 9/10 ma typ/max ai dd 3 (differential amplifier) av dd 3 = 5 v, both modes 41/44 ma typ/max di dd both modes 63/70 ma typ/max digital i/o mclk input amplitude 4 5 v typ input capacitance 7.3 pf typ input leakage current 5 a max three-state leakage current (d15:d0) 5 a max v inh 0.7 v drive v min v inl 0.3 v drive v max v oh 5 1.5 v min v oh 6 2.4 v typ v ol 4 0.1 v max 1 see the terminology section. 2 snr specifications in decibels are referred to a full-scale input, fs. tested with an input signal at 0.5 db below full scale, unless otherwise specified. 3 current scales with iclk frequency. see the typical performance characteristics section. 4 although the ad7760 can function with an mcl k amplitude of less than 5 v, this is the recommended amplitude to achieve the per formance as stated. 5 tested using the minimum v drive voltage of 1.65 v with a 400 a load current. 6 tested using v drive = 2.5 v with a 400 a load current.
ad7760 rev. a | page 6 of 36 timing specifications av dd 1 = dv dd = v drive = 2.5 v, av dd 2 = av dd 3 = av dd 4 = 5 v, t a = 25c, normal mode, unless otherwise noted. table 3. parameter limit at t min , t max unit description f mclk 1 mhz min applied master clock frequency 40 mhz max f iclk 500 khz min internal modulator clock derived from mclk 20 mhz max t 1 1 , 2 0.5 t iclk typ drdy pulse width t 2 10 ns min drdy falling edge to cs falling edge t 3 3 ns min rd /wr setup time to cs falling edge t 4 (0.5 t iclk ) + 16 ns max data access time t 5 t iclk min cs low read pulse width t 6 t iclk min cs high pulse width between reads t 7 3 ns min rd /wr hold time to cs rising edge t 8 11 ns max bus relinquish time t 9 2 0.5 t iclk typ drdy high period t 10 2 0.5 t iclk typ drdy low period t 11 (0.5 t iclk ) + 16 ns max data access time t 12 3 , 4 23 ns min data valid prior to drdy rising edge t 13 3 , 4 19 ns min data valid after drdy rising edge t 14 11 ns max bus relinquish time t 15 4 t iclk min cs low write pulse width t 16 4 t iclk min cs high period between address and data t 17 5 ns min data setup time t 18 0 ns min data hold time t 19 4 , 5 23 ns min data valid prior to mclk falling edge while drdy is logic low t 20 4 , 5 19 ns min data valid after mclk falling edge while drdy is logic low 1 t iclk = 1/f iclk . 2 when iclk = mclk, drdy pulse width depends on the mark-space ratio of applied mclk. 3 valid when using the modulator output mode with cdiv = 1. 4 see the modulator data output mo de section for timing diagrams. 5 valid when using the modulator output mode with cdiv = 0.
ad7760 rev. a | page 7 of 36 timing diagrams data msw lsw + status t 5 t 8 t 7 t 6 t 3 t 4 t 2 t 1 d[0:15] cs rd/wr drdy 04975-002 figure 2. filtered outputpar allel interface timing diagram t 15 d[0:15] cs rd/wr t 16 t 17 t 18 register address register data 04975-004 figure 3. ad7760 register write
ad7760 rev. a | page 8 of 36 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameters rating av dd 1 to gnd ?0.3 v to +3 v av dd 2:av dd 4 to gnd ?0.3 v to +6 v dv dd to gnd ?0.3 v to +3 v v drive to gnd ?0.3 v to +3 v v in +, v in C to gnd 1 ?0.3 v to +6 v v in a+, v in a? to gnd 1 ?0.3 v to +6 v digital input voltage to gnd 2 ?0.3 v to dv dd + 0.3 v mclk to mclkgnd ?0.3 v to +6 v v ref+ to gnd 3 ?0.3 v to av dd 4 + 0.3 v agnd to dgnd ?0.3 v to +0.3 v input current to any pin except supplies 4 10 ma operating temperature range commercial ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c tqfp exposed paddle package ja thermal impedance 92.7c/w jc thermal impedance 5.1c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c esd 600 v 1 absolute maximum voltage for v in ?, v in + and v ina ?, v ina + is 6.0 v or av dd 3 + 0.3 v, whichever is lower. 2 absolute maximum voltage on digital inputs is 3.0 v or dv dd + 0.3 v, whichever is lower. 3 absolute maximum voltage on v ref+ input is 6.0 v or av dd 4 + 0.3 v, whichever is lower. 4 transient currents of up to 200 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7760 rev. a | page 9 of 36 pin configuration and fu nction descriptions 64 dgnd 63 v drive 62 dgnd 61 db0 60 db1 59 db2 58 db3 57 db4 56 db5 55 db6 54 db7 53 dgnd 52 db8 51 db9 50 db10 49 db11 47 db13 46 db14 45 db15 42 dgnd 43 dgnd 44 v drive 48 db12 41 dv dd 40 cs 39 rd/wr 37 reset 36 sync 35 dgnd 34 agnd1 33 av dd 1 38 drdy 2 mclkgnd 3 mclk 4 av dd 2 7 agnd1 6 av dd 1 5 agnd2 1 dgnd 8 decapa 9 refgnd 10 v ref+ 12 av dd 4 13 agnd2 14 av dd 2 15 av dd 2 16 agnd2 11 agnd4 pin 1 17 r bias 18 agnd2 19 v in a+ 20 v in a? 21 v out a? 22 v out a+ 23 agnd3 24 av dd 3 25 v in + 26 v in ? 27 av dd 2 28 agnd2 29 agnd3 30 decapb 31 agnd3 32 agnd3 ad7760 top view (not to scale) 0 4975-005 figure 4. 64-lead t qfp pin configuration table 5. pin function descriptions pin no. mnemonic description 6, 33 av dd 1 2.5 v power supply for modulator. these pins should be decoupled to agnd1 (pin 7 and pin 34, respectively) with 100 nf and 10 f capacitors on each pin. see the decoupling and layout recommendations section for details. 4, 14, 15, 27 av dd 2 5 v power supply. these pins should be decoupled to agnd2 (pin 5 and pin 13, with 100 nf capacitors on each of pin 4, pin 14, and pin 15). pin 27 should be connected to pin 14 via a 15 nh inductor. see the decoupling and layout recommendations section for details. 24 av dd 3 3.3 v to 5 v power supply for differential amplifier. th is pin should be decoupled to agnd3 (pin 23) with a 100 nf capacitor. see the decoupling and layout recommendations section for details. 12 av dd 4 3.3 v to 5 v power supply for reference buffer. this pi n should be decoupled to pin 9 with a 10 nf capacitor in series with a 10 resistor. 7, 34 agnd1 power supply ground for analog circuitry powered by av dd 1. 5, 13, 16, 18, 28 agnd2 power supply ground for analog circuitry powered by av dd 2. 23, 29, 31, 32 agnd3 power supply ground for analog circuitry powered by av dd 3. 11 agnd4 power supply ground for analog circuitry powered by av dd 4. 9 refgnd reference ground. ground connection for the reference voltage. 41 dv dd 2.5 v power supply for digital circuitry and fir filter . this pin should be decoupled to dgnd with a 100 nf capacitor. 44, 63 v drive logic power supply input, 1.8 v to 2.5 v. the voltage supplied at these pins determines the operating voltage of the logic interface. both of these pins must be connected together and tied to the same supply. each pin should also be decoupled to dgnd with a 100 nf capacitor. 1, 35, 42, 43, 53, 62, 64 dgnd ground reference for digital circuitry. 19 v in a+ positive input to differential amplifier. 20 v in a? negative input to differential amplifier. 21 v out a? negative output from differential amplifier. 22 v out a+ positive output from differential amplifier. 25 v in + positive input to the modulator. 26 v in ? negative input to the modulator. 10 v ref+ reference input. the input range of this pin is determined by the reference buffer supply voltage (av dd 4). see the reference voltage filtering section for more details. 8 decapa decoupling pin. a 100 nf capacitor must be inserted between this pin and agnd.
ad7760 rev. a | page 10 of 36 pin no. mnemonic description 30 decapb decoupling pin. a 33 pf capacitor mu st be inserted between this pin and agnd3. 17 r bias bias current setting pin. a resistor must be inserted between this pin and agnd. for more details, see the bias resistor selection section. 45 to 52, 54 to 61 db15:db8, db7:db0 16-bit bidirectional data bus. these are three-state pins that are controlled by the cs pin and the rd /wr pin. the operating voltage for these pins is determined by the v drive voltage. see the modulator data output mode and ad7760 interface sections for more details. 37 reset a falling edge on this pin resets all internal digital circuitry and powers down the part. holding this pin low keeps the ad7760 in a reset state. 3 mclk master clock input. a low jitter, buffered digital cloc k must be applied to this pin. the output data rate depends on the frequency of this clock. see the clocking the ad7760 section for more details. 2 mclkgnd master clock ground sensing pin. 36 sync synchronization input. a falling edge on this pin resets the internal filt er. this can be used to synchronize multiple devices in a system. see the synchronization section for more details. 39 rd /wr read/write input. this pin, in conjunction with the ch ip select pin, is used to read and write data to and from the ad7760. if this pin is low when cs is low, a read takes place. if this pin is high when cs is low, a write occurs. see the modulator data output mode and ad7760 interface sections for more details. 38 drdy data ready output. each time new conversion data is av ailable, an active low pulse, ? iclk period wide, is produced on this pin. see the modulator data output mode and ad7760 interface sections for more details. 40 cs chip select input. used in conjunction with the rd /wr pin to read and write data from and to the ad7760. see the modulator data output mode and ad7760 interface sections for more details.
ad7760 rev. a | page 11 of 36 terminology signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the ad7760, it is defined as () 1 6 54 32 v vvvvv thd 22222 log20db ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second to the sixth harmonics. nonharmonic spurious-free dynamic range (sfdr) sfdr is the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component, excluding harmonics. dynamic range dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. the value for the dynamic range is expressed in decibels. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to 0. for example, the second- order terms include (fa + fb) and (fa ? fb), and the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7760 is tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero error zero error is the difference between the ideal midscale input voltage (when both inputs are sh orted together) and the actual voltage producing the midscale output code. zero error drift zero error drift is the change in the actual zero error value due to a temperature change of 1c. it is expressed as a percentage of full scale at room temperature. gain error the first transition (from 100 000 to 100 001) should occur for an analog voltage ? lsb above the nominal negative full scale. the last transition (from 011 110 to 011 111) should occur for an analog voltage 1? lsb below the nominal full scale. the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition, from the difference between the ideal levels. gain error drift gain error drift is the change in the actual gain error value due to a temperature change of 1c. it is expressed as a percentage of full scale at room temperature.
ad7760 rev. a | page 12 of 36 typical performance characteristics av dd 1 = dv dd = v drive = 2.5 v, av dd 2 = av dd 3 = av dd 4 = 5 v, v ref = 4.096 v, t a = 25c, normal mode, unless otherwise noted. all ffts are generated from 65,536 samples using a 7-term blackman-harris window. 04975-006 0 4000 8000 12000 16000 20000 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 24000 frequency (hz) amplitude (db) figure 5. normal mode fft, 1 khz, ?0.5 db input tone, 256 decimation 04975-007 0 4000 8000 12000 16000 20000 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 24000 frequency (hz) amplitude (db) figure 6. normal mode fft, 1 khz, ?6 db input tone, 256 decimation 0 4 9 7 5 - 0 0 8 0 4000 8000 12000 16000 20000 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 24000 frequency (hz) amplitude (db) figure 7. normal mode fft, 1 khz, ?60 db input tone, 256 decimation 04975-009 0 4000 8000 12000 16000 20000 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 24000 frequency (hz) amplitude (db) figure 8. low power fft, 1 khz, ?0.5 db input tone, 256 decimation 04975-010 0 4000 8000 12000 16000 20000 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 24000 frequency (hz) amplitude (db) figure 9. low power fft, 1 khz, ?6 db input tone, 256 decimation 04975-011 0 4000 8000 12000 16000 20000 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 24000 frequency (hz) amplitude (db) figure 10. low power fft, 1 khz, ?60 db input tone, 256 decimation
ad7760 rev. a | page 13 of 36 04975-012 0 250 500 750 1000 1250 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 frequency (khz) amplitude (db) figure 11. normal mode fft, 100 khz, ?0.5 db input tone, 8 decimation 04975-013 0 250 500 750 1000 1250 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 frequency (khz) amplitude (db) figure 12. normal mode fft, 100 khz, ?6 db input tone, 8 decimation 04975-014 0 250 500 750 1000 1250 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 frequency (khz) amplitude (db) figure 13. normal mode fft, 1 mhz, ?0.5 db input tone, 8 decimation 04975-015 0 250 500 750 1000 1250 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 frequency (khz) amplitude (db) figure 14. low power fft, 100 khz, ?0 .5 db input tone, 8 decimation 04975-016 0 250 500 750 1000 1250 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 frequency (khz) amplitude (db) figure 15. low power fft, 100 khz, ?6 db input tone , 8 decimation 04975-017 0 250 500 750 1000 1250 ?200 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 frequency (khz) amplitude (db) figure 16. low power fft, 1 mhz, ?0.5 db input tone, 8 decimation
ad7760 rev. a | page 14 of 36 0 ?200 0 1250 04975-018 frequency (khz) amplitude (db) ?25 ?50 ?75 ?100 ?125 ?150 ?175 250 500 750 1000 figure 17. normal mode fft, 1 mhz, ?6 db input tone, 8 decimation 0 ?200 0 1250 04975-019 frequency (khz) amplitude (db) ?25 ?50 ?75 ?100 ?125 ?150 ?175 250 500 750 1000 tone a: 999.75khz tone b: 1.00025mhz figure 18. normal mode imd, 1 mhz center frequency, 8 decimation 0 ?160 0 10000 04975-020 frequency (khz) amplitude (db) ?20 ?40 ?60 ?80 ?100 ?120 ?140 2000 4000 6000 8000 tone a: 999.75khz tone b: 1.00025mhz second-order imd: ?105.6db figure 19. normal mode imd, 1 mhz center frequency, 8 decimation 0 ?200 0 1250 04975-021 frequency (khz) amplitude (db) ?25 ?50 ?75 ?100 ?125 ?150 ?175 250 500 750 1000 figure 20. low power fft, 1 mhz, ?6 db input tone, 8 decimation 0 ?200 0 1250 04975-022 frequency (khz) amplitude (db) ?25 ?50 ?75 ?100 ?125 ?150 ?175 250 500 750 1000 tone a: 999.75khz tone b: 1.00025mhz figure 21. low power imd, 1 mhz center frequency, 8 decimation 0 ?160 0 10000 04975-023 frequency (khz) amplitude (db) ?20 ?40 ?60 ?80 ?100 ?120 ?140 2000 4000 6000 8000 tone a: 999.75khz tone b: 1.00025mhz second-order imd: ?115.7db figure 22. low power imd, 1 mhz center frequency, 8 decimation
ad7760 rev. a | page 15 of 36 0 ?160 995 1005 04975-024 frequency (khz) amplitude (db) ?20 ?40 ?60 ?80 ?100 ?120 ?140 997 999 1001 1003 tone a: 999.75khz tone b: 1.00025mhz third-order imd: ?89.15db figure 23. normal mode imd, 1 mhz center frequency, 8 decimation 100.5 96.5 04 0 04975-025 mclk frequency (mhz) snr (dbfs) 100.0 99.5 99.0 98.5 98.0 97.5 97.0 10 20 30 low power mode normal mode figure 24. snr vs. mclk frequency, 8 decimation, ?6 db, 1 khz input tone 120 95 0 256 04975-026 decimation rate snr (dbfs) 115 110 105 100 64 128 192 ?0.5db ?6db ?60db figure 25. normal mode snr vs. de cimation rate, 1 khz input tone 0 ?160 995 1005 04975-027 frequency (khz) amplitude (db) ?20 ?40 ?60 ?80 ?100 ?120 ?140 997 999 1001 1003 tone a: 999.75khz tone b: 1.00025mhz third-order imd: ?87.67db figure 26. normal mode imd, 1 mhz center frequency, 8 decimation ? 105 ?117 04 0 04975-028 mclk frequency (mhz) thd (dbc) ?107 ?109 ?111 ?113 ?115 10 20 30 normal mode low power mode figure 27. thd vs. mclk frequency, 8 decimation, ?6 db, 1 khz input tone 116 96 0 256 04975-029 decimation rate snr (dbfs) 112 108 104 100 64 128 192 ?0.5db ?6db ?60db figure 28. low power snr vs. deci mation rate, 1 khz input tone
ad7760 rev. a | page 16 of 36 4500 0 8385222 04975-030 24-bit code occurrence 4000 3500 3000 2500 2000 1500 1000 500 8385238 8385254 8385270 figure 29. normal mode, 24-bit histogram, 256 decimation 600 0 8385016 04975-031 24-bit code occurrence 500 400 300 200 100 8385116 8385216 8385416 8385316 8385516 figure 30. normal mode, 24-bit histogram, 8 decimation 0.0010 ?0.0010 0 1677721 6 04975-034 24-bit code inl (%) 0.0005 0 ?0.0005 4194304 8388608 12582912 +25c ?40c +85c figure 31. 24-bit inl, normal mode 3000 0 8383530 04975-032 24-bit code occurrence 2500 2000 1500 1000 500 83835246 8383562 8383578 8383594 8383610 figure 32. low power, 24-bit histogram, 256 decimation 450 0 8383236 04975-033 24-bit code occurrence 8383386 8383536 8383686 8383836 400 350 300 250 200 150 100 50 figure 33. low power, 24-bit histogram, 8 decimation 0.0015 ?0.0010 0 1677721 6 04975-036 24-bit code inl (%) 0.0005 0.0010 0 ?0.0005 4194304 8388608 12582912 +25c ?40c +85c figure 34. 24-bit inl, low power mode
ad7760 rev. a | page 17 of 36 0.6 ?0.6 0 1677721 6 04975-035 24-bit code dnl (lsb) 4194304 8388608 12582912 0.4 0.2 0 ?0.2 ?0.4 figure 35. 24-bit dnl 04975-057 02 0 0 40 iclk frequency (mhz) ai dd 2 (ma) 35 30 25 20 15 10 5 2 4 6 8 10 12 14 16 18 0 figure 36. ai dd 2 vs. iclk frequency (av dd 2 = 5 v) 04975-058 02 0 60 iclk frequency (mhz) di dd (ma) 2 4 6 8 10 12 14 16 18 50 40 30 20 10 figure 37. decimate 8, di dd vs. iclk frequency (dv dd = 2.5 v) 04975-059 02 0 50 iclk frequency (mhz) di dd (ma) 0 2 4 6 8 10 12 14 16 18 45 40 35 30 25 20 15 10 5 figure 38. decimate 32, di dd vs. iclk frequency (dv dd = 2.5 v) 04975-060 02 0 0 45 iclk frequency (mhz) di dd (ma) 40 35 30 25 20 15 10 5 2 4 6 8 10 12 14 16 18 figure 39. decimate 256, di dd vs. iclk frequency (dv dd = 2.5 v)
ad7760 rev. a | page 18 of 36 theory of operation the ad7760 employs a - conversion technique to convert the analog input into an equivalent digital word. the modulator samples the input waveform and outputs an equivalent digital word to the digital filter at a rate equal to iclk. by employing oversampling, the quantization noise is spread across a wide bandwidth from 0 to f iclk . this means that the noise energy contained in the signal band of interest is reduced (see figure 40 a). to further reduce the quantization noise in the signal band of interest, a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the signal band (see figure 40 b). the digital filtering that follows the modulator removes the large out-of-band quantization noise (see figure 40 c) while also reducing the data rate from f iclk at the input of the filter to f iclk /8 or less at the output of the filter, depending on the decimation rate used. digital filtering has certain advantages over analog filtering: it does not introduce significant noise or distortion and can be made perfectly linear in terms of phase. the ad7760 employs three fir filters in series. by using different combinations of decimation ratios, filter selection, and bypassing, data can be obtained from the ad7760 at a large range of data rates. multibit data from the modulator can be obtained at the iclk rate (see modulator data output mode section). the first filter receives the data from the modulator at a maximum frequency of 20 mhz and decimates it by 4 to output the data at 5 mhz. the partially filtered data can be output at this stage. the second filter allows the decimation rate to be chosen from 2 to 32 or to be completely bypassed. the third filter has a fixed decimation rate of 2, is user programmable, and has a default configuration. it is described in detail in the programmable fir filter section. this filter can also be bypassed. table 6 shows some characteristics of the default filter. the group delay of the filter is defined to be the delay to the center of the impulse response and is equal to the computation plus the filter delays. the delay until valid data is available (the dvalid status bit is set) is equal to twice the filter delay plus the computation delay. quantization noise f iclk \2 band of interest a. f iclk \2 noise shaping band of interest b. f iclk \2 band of interest digital filter cutoff frequency c. 04975-037 figure 40. - adc table 6. configuration with default filter iclk frequency filter 1 filter 2 filter 3 data state computation delay filter delay pass-band bandwidth output data rate (odr) 20 mhz bypassed bypassed bypassed unfiltered 0 0 10 mhz 20 mhz 20 mhz 4 bypassed bypassed partially fi ltered 0.325 s 1.2 s 1.35 mhz 5 mhz 20 mhz 4 bypassed 2 fully filtered 1.075 s 10.8 s 1 mhz 2.5 mhz 20 mhz 4 2 bypassed partially filtered 1.35 s 3.6 s 562.5 khz 2.5 mhz 20 mhz 4 2 2 fully filtered 1.625 s 22.8 s 500 khz 1.25 mhz 20 mhz 4 4 bypassed partially filtered 1.725 s 6 s 281.25 khz 1.25 mhz 20 mhz 4 4 2 fully filtered 1.775 s 44.4 s 250 khz 625 khz 20 mhz 4 8x bypassed partially filtered 2.6 s 10.8 s 140.625 khz 625 khz 20 mhz 4 8 2 fully filtered 2.25 s 87.6 s 125 khz 312.5 khz 20 mhz 4 16 bypassed partially filtered 4.175 s 20.4 s 70.3125 khz 312.5 khz 20 mhz 4 16 2 fully filtered 3.1 s 174 s 62.5 khz 156.25 khz 20 mhz 4 32 bypassed partially filtered 7.325 s 39.6 s 35.156 khz 156.25 khz 20 mhz 4 32 2 fully filtered 4.65 s 346.8 s 31.25 khz 78.125 khz 12.288 mhz 4 8 2 fully filtered 3.66 s 142.6 s 76.8 khz 192 khz 12.288 mhz 4 16 2 fully filtered 5.05 s 283.2 s 38.4 khz 96 khz 12.288 mhz 4 32 bypassed partially filtered 11.92 s 64.45 s 21.6 khz 96 khz 12.288 mhz 4 32 2 fully filtered 7.57 s 564.5 s 19.2 khz 48 khz
ad7760 rev. a | page 19 of 36 modulator data output mode operating the ad7760 in modulator output mode enables the output of data directly from the - modulator. this mode of operation bypasses the ad7760 on-board digital filtering capabilities, outputting data in its unfiltered form. as discussed in the theory of operation section, the ad7760 operates using oversampling, which spreads quantization noise over a wide bandwidth. the decrease in the quantization noise energy in the resulting signal band is illustrated in figure 40 a. by coupling the use of oversampling with the use of a high order, multibit - modulator, the ad7760 further reduces the quantization noise in the signal band. figure 41 is an fft of unfiltered data output from the ad7760 when it is used in modulator output mode. this clearly demonstrates the shaping of the quantization noise performed by the ad7760s - modulator. modulator inputs the maximum voltage input to each differential modulator input pin is 0.8 4.096 v 3.275 v (80% of v ref ), which must sit on a common mode of v ref /2. this maximum differential input voltage is shown as the conditioned output of the ad7760s on-board differential amplifier in figure 52 in the driving the ad7760 section. further details on the signal conditioning implemented by the ad7760s on-board differential amplifier and the recommended external circuitry that accompanies it is described in the driving the ad7760 section. 0 ?160 01 frequency (mhz) amplitude (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 123456789 04975-048 figure 41. fft of data output by th e ad7760 in modulator output mode modulator data output scaling in modulator output mode, data is output in a 16-bit twos complement format on pins d [15:0]; however, this data is scaled to 15 bits. the transfer function in figure 42 shows the scaling involved for the 16 data bits output from modulator pins d[15:0] vs. the maximum differential voltage input allowed for the modulator inputs (v in + and v in ?). d[15:0] 0011 0011 0011 0010 0011 1111 1111 1111 0000 0000 0000 0000 1100 1100 1100 1100 1100 0000 0000 0000 +4.096v ?4.096v v in + = 3.6855v v in ? = 0.4105v +3.275v = modulator full scale = 80% of +4.096v 80% of +4.096v = modulator full scale = ?3.275v v in +=2.048v v in ? = 2.048v v in + = 0.4105v v in ? = 3.6855v 04975-049 figure 42. modulator output data scaling as the nature of the modulator output is coarse relative to the fully filtered output of the ad7760 (due to the associated quantization noise of the modulator output), bits d[3:0] of the modulator output are zero when operating in modulator data output mode. thus, the data outputs for the calculations listed in example 1 and example 2 for inputs to the modulator pins v in + and v in ? show bits d[3:0] of the modulator output as zero. example 1 v in + = 3.5 v v in ? = 0.595 v modulator output code = ([v in (+) ? v in (?)]/4.096 v) 16384 = [(3.5 v ? 0.595 v)/4.096 v] 16384 = +11620 direct scaling: [0010 1101 0110 0100] value output on data output pins d[15:0]: d [15:0] = [0010 1101 0110 0000]. example 2 v in + = 0.595 v v in ? = 3.5 v modulator output code = ([v in (+) ? v in (?)]/4.096 v) 16384 = [(0.595 v ? 3.5 v)/4.096 v] 16384 = ?11620 direct scaling: [1101 0010 1001 1100] value output on data output pins d[15:0]: d [15:0] = [1101 0010 1001 0000].
ad7760 rev. a | page 20 of 36 modulator data output mode interface the ad7760 can be configured in modulator data output mode (bypassing the default decimation filtering) by writing 0 to each of the bits contained in control register 1: byp f1 , byp f3 , and dec [2:0]. this will bypass all digital decimation filtering offered by the ad7760. see the ad7760 registers section for further details. when the ad7760 is operating in modulator data output mode, a different parallel interfacing scheme than that used for config- urations, where the ad7760s data output is filtered is necessary. the data output rate depends on the clock divider ratio that is used. when the cdiv bit in control register 2 is set to logic high, data is output at the mclk frequency. if the cdiv bit is set to logic low, data is output at a frequency of mclk/2. see the clocking the ad7760 section. clock divide-by-1 mode (cdiv = 1) when obtaining data from the ad7760 in modulator output mode, both the rd /wr and cs lines must be held low. this brings the data bus out of its high impedance state. figure 43 shows the timing diagram for reading data in the modulator data output mode when operating with cdiv = 1 (that is, iclk = mclk). a drdy pulse is generated for each word. the data on each of the 16 data output pins, d [15:0], is valid on the rising edge of the drdy pulse. the drdy pulse can be used to latch the modulator data into a fifo or as a dma control signal. shortly after the rd /wr and cs lines return high, the ad7760 stops outputting data and the data bus returns to high impedance. clock divide-by-2 mode (cdiv = 0) when operating in modulator output mode with cdiv = 0 (that is, iclk = mclk/2), the frequency of the drdy signal created is half that of the mclk frequency input to the device. the timing scheme that is used when cdiv = 0 depends on the number of mclk cycles that occur between reset and sync . if the number of mclk cycles (n) between the rising edge of reset and the rising edge of sync (see figure 44 ) is an even value, use the interface timing shown in figure 43 . if n is an odd value, use the interface timing shown in figure 45 . t 9 t 10 t 14 t 11 t 12 t 13 drdy cs, rd/wr d[0:15] invalid data mod data m mod data m + 1 mod d... 04975-050 figure 43. ad7760 modulator output mode ( cdiv = 1) and ( cdiv = 0, n is even) mclk reset sync n t mclk 04975-051 figure 44. ad7760 relative timing between reset and sync in modulator output mode cdiv = 0
ad7760 rev. a | page 21 of 36 invalid data mod data m mod data m + 1 mod d... t 9 t 10 t 20 drdy d[0:15] mclk cs, rd/wr t 11 t 19 t 14 04975-052 figure 45. ad7760 modulator output mode ( cdiv = 0, n is odd) in the case where n is an odd number of mclk cycles, the modulator data output on pins d [15:0] is output on the rising edge of drdy . in this case, the modulator data should be read on the falling edge of mclk when drdy is logic low. figure 45 shows timing details to be used when reading the modulator output data where cdiv = 0 and there is an odd number of mclk cycles between the rising edge of reset and the rising edge of sync . the edge of mclk that should be used under these conditions is illustrated in figure 45 by arrows on the mclk falling edges in question. using the ad7760 in modulator output mode the following is the recommended sequence for powering up and using the ad7760: 1. apply power. 2. start the clock oscillator, applying mclk. 3. ta ke reset low for a minimum of one mclk cycle. 4. wait a minimum of two mclk cycles after the rising edge of reset . 5. write to control register 2 to power up the adc and the differential amplifier as required. the correct clock divider ( cdiv ) ratio should be programmed at this time. 6. write to control register 1 to set the bypass filter bits, byp f1 and byp f3 , and the decimation rate bits, dec [2:0], to 0. 7. wait a minimum of six mclk cycles after the rising edge of cs has been released. 8. ta ke sync low for a minimum of four mclk cycles, if required, to synchronize multiple parts. using this sequence results in an even number of mclk cycles between the rising edge of reset and the rising edge of sync . therefore, when using this sequence with cdiv = 0, the interface timing shown in figure 43 should be implemented. note that whether the number of mclk cycles between the rising edge of reset and sync is odd or even is irrelevant when the ad7760 is operated with cdiv = 1. when using the ad7760 in modulator output mode, the offset, gain, and overrange registers are not operational. the only registers that can be used are control register 1 and control register 2.
ad7760 rev. a | page 22 of 36 ad7760 interface reading data when the ad7760 is outputting data at a 5 mhz output data rate or less, the interface operates in a conventional mode, as shown in figure 2 , using a 16-bit bidirectional parallel interface. this interface is controlled by the rd /wr and cs pins. the 24-bit conversion data is output in twos complement format. when a new conversion result is available, an active low pulse is output on the drdy pin. to read a conversion result from the ad7760, two 16-bit read operations are performed. the drdy pulse indicates that a new conversion result is available. both rd /wr and cs go low to perform the first read operation. shortly after both lines go low, the data bus becomes active and the 16 most significant bits (msbs) of the conversion result are output. the rd /wr and cs lines must return high for a full iclk period before the second read is performed. this second read contains the eight least significant bits (lsbs) of the conversion result along with six status bits. these status bits are shown in table 7 . descriptions of the other status bits are found in table 17 . table 7. status bits during data read msb lsb d7 d6 d5 d4 d3 d2 d1 d0 dvalid ovr ufilt lpwr filtok dlok 0 0 shortly after rd /wr and cs return high, the data bus returns to a high impedance state. both read operations must be completed before a new conversion result is available because the new result overwrites the contents of the output register. if a drdy pulse occurs during a read operation, the data read is invalid. reading status and other registers the ad7760 features a number of programmable registers. to read back the contents of these registers or the status register, the user must first write to the control register of the device, setting a bit that corresponds to the register to be read. the next read operation outputs the contents of the selected register instead of a conversion result. the ad7760 registers section provides more information on the relevant bits in the control register. sharing the parallel bus by its nature, the high accuracy of the ad7760 makes it sensitive to external noise sources. these include digital activity on the parallel bus. for this reason, it is recommended that the ad7760 data lines be isolated from the system data bus by means of a latch or buffer to ensure all digital activity on the d0 to d15 pins is controlled by the ad7760. if multiple synchronized ad7760 parts that share a properly distributed common mclk signal exist in a system, these parts can share a common bus without being isolated from each other. this bus can then be isolated from the system bus by a single latch or buffer. synchronization the sync input to the ad7760 provides a synchronization function that allows the user to begin gathering samples of the analog front-end input from a known point in time. the sync function allows multiple ad7760s, operated from the same mclk, reset , and sync signals, to be synchronized so that each adc simultaneously updates its output register. the distribution of the signals that are common to each of the devices that are to be synchronized is extremely important in ensuring that the timing of each of the ad7760 devices is correct, that is, that each ad77 60 device sees the same digital edges synchronously. the sync signal is sensed on the falling edge of mclk. on the first falling edge of mclk after sync goes logic low, the digital filter sequencer is reset to 0. the filter is held in a reset state until a falling edge of the mclk senses sync logic high. the sync signal must remain logic low for a minimum of four mclk cycles. figure 46 shows the recommended timing for the sync signal with respect to mclk. device synchronized from this point in time mclk sync 4 t mclk minsynclogiclow 04975-053 figure 46. recommended sync timing the rising edge of sync should be coincident with the rising edge of mclk. thus, the next falling edge of mclk senses sync logic high and takes the filter out of its reset state. by applying this signal scheme to multiple adcs using the same mclk and sync signals, all of the devices will gather input samples synchronously. following a sync signal, the digital filter needs time to settle before valid data can be read from the ad7760. the dvalid status bit (d7 in table 7 ) output with each conversion indicates when valid data is being output by the converter. the time from the rising edge of sync until the dvalid bit is asserted is dependent on the filter configuration used. see the theory of operation section and the values listed in table 6 for details on calculating the time until dvalid is asserted.
ad7760 rev. a | page 23 of 36 writing to the ad7760 there are many features and parameters that the user can change by writing to the ad7760 device. see the using the ad7760 section, which details the writing sequence needed to initialize the operation of the part. the ad7760 has programmable registers that are 16 bits wide. this means that two write operations are required to program a register. the first write contains the register address, and the second write contains the register data. an exception is when a user-defined filter is being downloaded to the ad7760. this is described in detail in the downloading a user-defined filter section. the ad7760 registers section contains the register addresses and details. figure 3 shows a write operation to the ad7760. the rd /wr line is held high while the cs line is brought low for a minimum of four iclk periods. the register address is latched during this period. the cs line is brought high again for a minimum of four iclk periods before the register data is put onto the data bus. if a read operation occurs between the writing of the register address and the register data, the register address is cleared and the next write must be the register address. this also provides a method to revert back to a known situation if the user forgets whether the next write is an address or data. generally, the ad7760 is written to and configured on power- up and very infrequently, if at all, after that. following any write operation, the full group delay of the filter must elapse before valid data is output from the ad7760.
ad7760 rev. a | page 24 of 36 clocking the ad7760 the ad7760 requires an external low jitter clock source. this signal is applied to the mclk pin, and the mclkgnd pin is used to sense the ground from the clock source. an internal clock signal (iclk) is derived from the mclk input signal. the iclk controls all internal operations of the ad7760. the maximum iclk frequency is 20 mhz, but due to an internal clock divider, a range of mclk frequencies can be used. there are two ways to generate the iclk: iclk = mclk ( cdiv = 1) iclk = mclk /2 ( cdiv = 0) these options are selected from the control register (see the ad7760 registers section for more details). on power-up, the default is iclk = mclk/2 to ensure that the part can handle the maximum mclk frequency of 40 mhz. for output data rates equal to those used in audio systems, a 12.288 mhz iclk frequency can be used. as shown in table 6 , output data rates of 192 khz, 96 khz, and 48 khz are achievable with this iclk frequency. as mentioned previously, this iclk frequency can be derived from different mclk frequencies. it is recommended that the mclk signal applied to the ad7760 has a 50-50 mark-space ratio. when operating in clock divide-by-1 mode (that is, cdiv = 1), using higher mark-space ratios reduces the maximum mc lk frequency that can be applied to the ad7760 yielding maximum performance. for example, using a mark-space ratio of 60-40 (with cdiv = 1) reduces the maximum mclk frequency that will yield the maximum inl and thd performance to 16 mhz. buffering the mclk signal the mclk signal for the ad7760 must be buffered before being input to the mclk pin on the ad7760 device. this can be done simply by routing the mclk signal to both inputs of an and gate (see figure 47 ). the recommended buffer is the nc7sz08m5, which is a two- input and gate from fairchild semiconductor. using the buffer with a supply voltage of 5 v is advised to achieve optimum performance from the ad7760. 3 mclk mclk source nc7sz08m5 (and gate) ad7760 04975-054 figure 47. buffering the mclk signal using the nc7sz08m5 and gate mclk jitter requirements the mclk jitter requirements depend on a number of factors and are given by 20 )( 10 2 )( dbsnr f osr t in rmsj = where: osr = oversampling ratio = f iclk /odr . f in = maximum input frequency. snr(db) = target snr. example 1 this example can be taken from table 6 , where: odr = 2.5 mhz. f iclk = 20 mhz. f in (max) = 1 mhz. snr = 108 db. ps79.1 10102 8 4.56 )( = = rms j t this is the maximum allowable clock jitter for a full-scale, 1 mhz input tone with the given iclk and output data rate. example 2 take a second example from table 6 , where: odr = 48 khz. f iclk = 12.288 mhz. f in (max) = 19.2 khz. snr = 120 db. ps133 10102.192 256 63 )( = = rms j t the input amplitude also has an effect on these jitter figures. for example, if the input level was 3 db below full-scale, the allowable jitter would be increased by a factor of 2, increasing the first example to 2.53 ps rms. this happens when the maximum slew rate is decreased by a reduction in amplitude. figure 48 and figure 49 illustrate this point, showing the maximum slew rate of a sine wave of the same frequency but with different amplitudes.
ad7760 rev. a | page 25 of 36 1.0 ? 1.0 0.5 0 ? 0.5 04975-038 figure 48. maximum slew rate of sine wave with amplitude of 2 v p-p 1.0 ? 1.0 0.5 0 ? 0.5 04975-039 figure 49. maximum slew rate of sine wave (with the same frequency as in figure 48 ) with amplitude of 1 v p-p
ad7760 rev. a | page 26 of 36 driving the ad7760 the ad7760 has an on-chip differential amplifier that operates with a supply voltage (av dd 3) within the 3.15 v to 5.25 v range. for a 4.096 v reference, the supply voltage must be 5 v. to achieve the specified performance in normal mode, the differential amplifier should be configured as a first-order antialias filter, as shown in figure 50 . any additional filtering should be carried out in previous stages using low noise, high performance op amps, such as the ad8021 . suitable component values for the first-order filter are listed in table 8 . using the values in the table as an example yields a 10 db attenuation at the first alias point of 19 mhz. a1 r in r fb c fb r in r m r m c s r fb c fb v in ? a b v in + 0 4975-040 figure 50. differential amplifier configuration table 8. normal mode component values v ref r in r fb r m c s c fb 4.096 v 1 k 655 18 5.6 pf 33 pf figure 52 shows the signal conditioning that occurs using the circuit shown in figure 50 with a 2.5 v input signal biased around ground and the component values and conditions listed in table 8 . the differential amplifier always biases the output signal to sit on the optimum common mode of v ref /2, in this case 2.048 v. the signal is also scaled to give the maximum allowable voltage swing with this reference value. this is calculated as 80% of v ref , that is, 0.8 4.096 v 3.275 v p-p on each input. with a 4.096 v reference, a 5 v supply must be provided to the reference buffer (av dd 4). with a 2.5 v reference, a 3.3 v supply must be provided to av dd 4. figure 51 shows the transfer function in terms of the 24-bit digital output codes (twos complement coding) of the ad7760 vs. the voltage signals v a and v b applied to the on-board differential amplifier a1, as shown in figure 52 . 011?111 011?110 000?010 000?001 000?000 111?111 111?110 100?000 100?001 24 bits ad7760 24-bit o utput b=+2.5v a = ?2.5v a=0v b=0v a=+2.5v b = ?2.5v 04975-056 figure 51. transfer function for the ad7760 filtered output where v a and v b are inputs to the on-board differential amplifier a1 +2.5v 0v ?2.5v a +2.5v 0v ?2.5v b inputs to the ad7760 differential amplifier outputs of the ad7760 differential amplifier +3.685v +2.048v +0.410v +3.685v +2.048v +0.410v v in + v in ? 0 4975-055 figure 52. differential amplifier signal conditioning
ad7760 rev. a | page 27 of 36 to obtain maximum performance from the ad7760, it is advisable to drive the adc with differential signals. figure 53 shows how a bipolar, single-ended signal biased around ground can drive the ad7760 with the use of an external op amp, such as the ad8021 . a1 r in r fb c fb r in r m r m c s r fb c fb v in ? v in v in + ad8021 2r 2r r 0 4975-042 figure 53. single-ended-t o-differential conversion the ad7760 employs a double-sampling front end, as shown in figure 54 . for simplicity, only the equivalent input circuit for v in + is shown. the equivalent input circuitry for v in ? is the same. cs2 cpb2 ss4 sh4 cpa ss2 sh2 cs1 cpb1 ss3 sh3 ss1 sh1 analog modulator v in + 04975-043 figure 54. equivalent input circuit sampling switches ss1 and ss3 are driven by iclk, whereas sampling switches ss2 and ss4 are driven by iclk . when iclk is high, the analog input voltage is connected to cs1. on the falling edge of iclk, the ss1 and ss3 switches open and the analog input is sampled on cs1. similarly, when iclk is low, the analog input voltage is connected to cs2. on the rising edge of iclk, the ss2 and ss4 switches open and the analog input is sampled on cs2. capacitors cpa, cpb1, and cpb2 represent parasitic capacitances that include the junction capacitances associated with the mos switches. table 9. equivalent component values mode cs1 (pf) cs2 (pf) cpa (pf) cpb1/2 (pf) normal 51 51 12 20 low power 13 13 12 5 using the ad7760 the following is the recommended sequence for powering up and using the ad7760: 1. apply power. 2. start the clock oscillator, applying mclk. 3. ta ke reset low for a minimum of one mclk cycle. 4. wait a minimum of two mclk cycles after reset has been released. 5. write to control register 2 to power up the adc and the differential amplifier as required. the correct clock divider ( cdiv ) ratio should be programmed at this time. 6. write to control register 1 to set the output data rate. 7. wait a minimum of five mclk cycles after cs has been released. 8. ta ke sync low for a minimum of four mclk cycles, if required, to synchronize multiple parts. data can then be read from the part using the default filter, offset, gain, and overrange threshold values. the conversion data read is not valid, however, until the group delay of the filter has elapsed. once this has occurred, the dvalid bit read with the data lsw is set, indicating that the data is indeed valid. the user can then download a different filter if required (see the downloading a user-defined filter section). values for gain, offset, and overrange threshold registers can be written or read at this stage.
ad7760 rev. a | page 28 of 36 decoupling and layout recommendations due to the high performance nature of the ad7760, correct decoupling and layout techniques are required to obtain the performan ce as stated within this data sheet. figure 55 shows a simplified connection diagram for the ad7760. v in a+ v in a? v out a? v out a+ v in a+ v in a? v out a? v out a+ decapa decapb v in + v in ? v ref+ v in + v in ? v refx refgnd r bias dgnd dgnd dgnd dgnd dgnd dgnd dgnd 19 20 21 22 8 30 25 26 10 9 17 1 35 42 43 53 62 64 db0 db2 db1 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db0 db2 db1 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 cs rd/wr reset sync drdy mclk mclkgnd cs rd/wr reset sync drdy mclk agnd1 agnd1 agnd2 agnd2 agnd2 agnd2 agnd2 agnd3 agnd3 agnd3 agnd3 agnd4 7 34 5 13 16 18 28 23 29 31 32 11 av dd 2 av dd 2 av dd 2 av dd 4 av dd 1 av dd 1 av dd 3 av dd 2 v drive v drive dv dd pin 1 4 pin 1 5 pin 4 pin 1 2 pin 6 pin 3 3 pin 2 4 pin 2 7 pin 4 4 pin 6 3 pin 41 14 15 4 12 6 33 24 27 44 63 41 ad7760bsv 61 60 59 58 55 54 50 49 46 45 40 37 36 38 3 2 57 56 52 51 48 47 39 r19 160k ? c64 33pf c7 100nf db [0:15] u2 av dd 3 pin 24 (vdif1) c54 100nf l6 dv dd pin 41 (dv dd ) c58 100nf l8 av dd 2 pin 4 (rhs) c48 100nf l1 pin 15 (vbias) c50 100nf l3 pin 14 (lhs) pin 27 c62 100nf l2 l9 av dd 4 pin 12 (vbuf) c59 10nf l4 r38 10 ? av dd 1 pin 5 (vmod1) c52 100nf l5 pin 33 (vmod2) c53 100nf l11 v drive pin 44 (vdrv1) c56 100nf l7 pin 63 (vdrv2) c57 100nf l12 04975-046 figure 55. simplified connection diagram
ad7760 rev. a | page 29 of 36 supply decoupling every supply pin must be connected to the appropriate supply via a ferrite bead and decoupled to the correct ground pin with a 100 nf, 0603 case size, x7r dielectric capacitor. there are two exceptions to this: ? pin 12 (av dd 4) must have a 10 resistor inserted between the pin and a 10 nf decoupling capacitor, which is connected to ground at pin 9. ? pin 27 (av dd 2) does not require a separate decoupling capacitor or a direct connection to the supply, but instead is connected to pin 14 via a 15 nh inductor. additional decoupling there are two other decoupling pins on the ad7760pin 8 (decapa) and pin 30 (decapb). pin 8 should be decoupled with a 100 nf capacitor, and pin 30 requires a 33 pf capacitor. reference voltage filtering a low noise reference source, such as the adr431 (2.5 v) or adr434 (4.096 v), is suitable for use with the ad7760. the reference voltage supplied to the ad7760 should be decoupled and filtered as shown in figure 56 . the recommended scheme for the reference voltage supply is a 100 series resistor connected to a 100 f tantalum capacitor, followed by a series resistor of 10 , and finally a 10 nf capacitor placed as close as possible to the v ref+ pin, decoupling this capacitor to the associated ground pin, pin 11. 7.5v pin 10 v out 2 v in 6 4 c15 10f c9 100nf r30 100 ? r17 10 ? + c46 10nf c11 100f + adr434 gnd u3 04975-047 figure 56. reference connection differential amplifier components the correct components for use around the on-chip differential amplifier are detailed in table 8 . matching the components on both sides of the differential amplifier is important to minimize distortion of the signal applied to the amplifier. a tolerance of 0.1% or better is required for these components. symmetrical routing of the tracks on both sides of the differential amplifier also assists in achieving the stated performance. bias resistor selection the ad7760 requires a resistor to be connected between the r bias and agnd pins. the value of this resistor is dependent on the reference voltage being applied to the device. the resistor value should be selected to produce a current of 25 a through the resistor to ground. for a 2.5 v reference voltage, the correct resistor value is 100 k, and for a 4.096 v reference, the correct resistor value is 160 k. layout considerations while using the correct components is essential to achieve optimum performance, the correct layout is just as important. the ad7760 product page on the analog devices website contains the gerber files for the ad7760 evaluation board. these files should be used as a reference when designing any system using the ad7760. the location and orientation of some of the components mentioned in previous sections of this data sheet are critical, and particular attention must be paid to the components that are located close to the ad7760. locating these components farther away from the device can have a direct impact on the achievable maximum performance. the use of ground planes should also be carefully considered. to ensure that the return currents through the decoupling capacitors are flowing to the correct ground pin, the ground side of the capacitors should be as close as possible to the ground pin associated with that supply. a ground plane should not be relied on as the sole return path for decoupling capacitors because the return current path using ground planes is not easily predictable. exposed paddle the ad7760 64-lead tqfp employs a 6 mm 6 mm exposed paddle (see figure 59 ). the paddle reduces the thermal resistance of the package by providing a path for heat energy to flow between the package and the pcb and, in turn, increases the heat transfer efficiency from the ad7760 package. connecting the exposed paddle to the agnd plane of the pcb is essential in creating the conditions that allow the ad7760 package to perform to the highest specifications possible. the exposed paddle should not be connected directly to any of the ground pins on the ad7760 and should only be connected to the analog ground plane. best practice is to use multiple vias connecting the exposed paddle to the agnd plane of the pcb.
ad7760 rev. a | page 30 of 36 programmable fir filter as previously mentioned, the third fir filter on the ad7760 is user programmable. the default coefficients that are loaded upon reset are given in table 10 , and the frequency responses are shown in figure 57 . the frequencies quoted in figure 57 scale directly with the output data rate. table 10. default filter coefficients no. dec value hex value no. dec value hex value 0 53656736 332bca0 24 700847 ab1af 1 25142688 17fa5a0 25 ?70922 401150a 2 ?4497814 444a196 26 ?583959 408e917 3 ?11935847 4b62067 27 ?175934 402af3e 4 ?1313841 4140c31 28 388667 5ee3b 5 6976334 6a734e 29 294000 47c70 6 3268059 31dddb 30 ?183250 402cbd2 7 ?3794610 439e6b2 31 ?302597 4049e05 8 ?3747402 4392e4a 32 16034 3ea2 9 1509849 1709d9 33 238315 3a2eb 10 3428088 344ef8 34 88266 158ca 11 80255 1397f 35 ?143205 4022f65 12 ?2672124 428c5fc 36 ?128919 401f797 13 ?1056628 4101f74 37 51794 ca52 14 1741563 1a92fb 38 121875 1dc13 15 1502200 16ebf8 39 16426 402a 16 ?835960 40cc178 40 ?90524 401619c 17 ?1528400 4175250 41 ?63899 400f99b 18 93626 16dba 42 45234 b0b2 19 1269502 135efe 43 114720 1c020 20 411245 6466d 44 102357 18fd5 21 ?864038 40d2f26 45 52669 cdbd 22 ?664622 40a242e 46 15559 3cc7 23 434489 6a139 47 1963 7ab the default filter should be sufficient for most applications. it is a standard brick wall filter with a symmetrical impulse response. the default filter has a length of 96, is nonaliasing, and provides 120 db of attenuation at nyquist. this filter not only performs signal antialiasing, but also suppresses out-of-band quantization noise produced by the analog-to-digital conversion process. any significant relaxation in the stop-band attenuation or transition bandwidth relative to the default filter can result in a failure to meet the snr specifications. the default filter characteristics scale with both the mclk frequency applied and the decimation rate chosen by the user. to create a filter, note the following: ? the filter must be an even, symmetrical fir. ? the coefficients are in sign-and-magnitude format, with 26 magnitude bits and sign coded as positive = 0. ? the filter length must be between 12 taps and 96 taps in steps of 12. ? because the filter is symmetrical, the number of coefficients that must be downloaded is half the filter length. the default filter coefficients exemplify this with only 48 coefficients listed for a 96-tap filter. ? coefficients are written from the center of the impulse response (adjacent to the point of symmetry) outwards. ? the coefficients are scaled so that the in-band gain of the filter is equal to 134,217,726, with the coefficients rounded to the nearest integer. for a low-pass filter, this is the equivalent of having the coefficients summed arithmetically (including sign) to a +67,108,863 (0x3ff ffff) positive value over the half-impulse-response coefficient set (a maximum of 48 coefficients). any deviation from this introduces a gain error. ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 0 500 2000 1500 1000 2500 frequency (khz) amplitude (db) 0 ?0.1db frequency = 1.004mhz pass-band ripple = 0.05db stop band = 1.25mhz ?3db frequency = 1.06mhz 04975-044 figure 57. default filter freq uency response (2.5 mhz odr) the procedure for downloading a user-defined filter is detailed in the downloading a user-defined filter section.
ad7760 rev. a | page 31 of 36 downloading a user-defined filter as previously mentioned, the filter coefficients are 27 bits in lengthone sign and 26 magnitude bits. because the ad7760 has a 16-bit parallel bus, the coefficients are padded with 5 msb 0s to generate a 32-bit word, split into two 16-bit words for downloading. the first 16-bit word for each coefficient becomes (00000, sign bit, magnitude [25:16]), whereas the second word becomes (magnitude [15:0]). to ensure that a filter is downloaded correctly, a checksum must also be generated and then downloaded following the final coefficient. the checksum is a 16-bit word generated by splitting each 32-bit word into four bytes and summing the bytes from all coefficients up to a maximum of 192 bytes (48 coefficients four bytes). the same checksum is generated internally in the ad7760 and compared with the downloaded checksum. the dl_ok bit in the status register is set if these two checksums agree. to download a user filter 1. write to control register 1, setting the dl_filt bit and the correct filter length bits corresponding to the length of the filter to be downloaded (see table 11 ). 2. write the first half of the current coefficient data (00000, sign bit, magnitude [25:16]). the first coefficient to be written must be the one adjacent to the point of filter symmetry. 3. write the second half of the current coefficient data (magnitude [15:0]). 4. repeat step 2 and step 3 for each coefficient. 5. write the 16-bit checksum. 6. use the following methods to verify that the filter coefficients are downloaded correctly: a. read the status register, checking the dl_ok bit. b. read data and observe the status of the dl_ok bit. note that because the user coefficients are stored in ram, they are cleared after a reset operation or a loss of power. table 11. filter length values flen [3:0] number of coefficients filter length 0000 default default 0001 6 12 0011 12 24 0101 18 36 0111 24 48 1001 30 60 1011 36 72 1101 42 84 1111 48 96 example filter download the following is an example of downloading a short user- defined filter with 24 taps. the frequency response is shown in figure 58 . 10 ?80 06 frequency (khz) amplitude (db) 0 0 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 100 200 300 400 500 04975-045 figure 58. 24-tap fir frequency response the coefficients for the filter are listed in table 12 and are shown from the center of symmetry outwards. the raw coefficients were generated using a commercial filter design tool and were scaled appropriately so that their sum equals 67,108,863 (0x3ff ffff). table 12. 24-tap fir coefficients coefficient raw scaled 1 0.365481974 53188232 2 0.201339905 29300796 3 0.009636604 1402406 4 ?0.075708848 ?11017834 5 ?0.042856209 ?6236822 6 0.019944246 2902466 7 0.036437914 5302774 8 0.007592007 1104856 9 ?0.021556583 ?3137108 10 ?0.024888355 ?3621978 11 ?0.012379538 ?1801582 12 ?0.001905756 ?277343
ad7760 rev. a | page 32 of 36 table 13 shows the hexadecimal values (in sign-and-magnitude format) that are downloaded to the ad7760 to realize this filter. the table is also split into the bytes that are summed to produce the checksum. the checksum generated from these coefficients is 0x0e6b. table 13. filter hexadecimal values word 1 word 2 coefficient byte 1 byte 2 byte 3 byte 4 1 03 2b 96 88 2 01 bf 18 3c 3 00 15 66 26 4 04 a8 1e 6a 5 04 5f 2a 96 6 00 2c 49 c2 7 00 50 e9 f6 8 00 10 db d8 9 04 2f de 54 10 04 37 44 5a 11 04 1b 7d 6e 12 04 04 3b 5f table 14 lists the 16-bit words the user would write to the ad7760 to set up the adc and download this filter, assuming an output data rate of 1.25 mhz has been selected. table 14. sequence of write in structions to set up device and download the filter example word description 0x0001 address of control register 1. 0x8079 control register data. dl filter: set filter length = 24, set output data rate = 1.25 mhz. 0x032b first coefficient, word 1. 0x9688 first coefficient, word 2. 0x01bf second coefficient, word 1. 0x183c second coefficient, word 2. other coefficients. 0x0404 twelfth (final) coefficient, word 1. 0x3b5f final coefficient, word 2. 0x0e6b checksum. wait (0.5 t iclk number of unused coefficients) for ad7760 to write 0s to the remaining unused coefficients. 0x0001 address of control register. 0x0879 control register data. set read status and maintain filter length and decimation settings. read contents of status register. check bit 7 (dl_ok) to determine if the filter was downloaded correctly.
ad7760 rev. a | page 33 of 36 ad7760 registers the ad7760 has a number of user-programmable registers. the control registers are used to set the decimation rate, the filter c onfiguration, the clock divider, and so on. there are also digital gain, offset, and overrange threshold registers. writing to these registers in volves writing the register address first, then a 16-bit data-word. register addresses, details of individual bits, and default values are giv en in this section. control register 1address 0x0001 default value 0x001a msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dl_ filt rd ovr rd gain rd off rd stat 0 sync flen3 flen2 flen1 flen0 byp f3 byp f1 dec2 dec1 dec0 table 15. bit descriptions of control register 1 bit mnemonic description 15 dl_filt 1 download filter. before downloading a user-defined filter, this bit must be set. the filter length bits must also be set at this time. the write operations that follo w are interpreted as the user coefficients for the fir filter until all the coefficients an d the checksum have been written. 14 rd ovr 1, 2 read overrange. if this bit has been set, the next read operation outputs the contents of the overrange threshold register instead of a conversion result. 13 rd gain 1, 2 read gain. if this bit has been set, the next read ope ration outputs the contents of the digital gain register. 12 rd off 1, 2 read offset. if this bit has been set, the next read ope ration outputs the contents of the digital offset register. 11 rd stat 1, 2 read status. if this bit has been set, the next read operation outputs the conten ts of the status register. 10 0 0 must be written to this bit. 9 sync 1 synchronize. setting this bit initiates an internal sync hronization routine. setting th is bit simultaneously on multiple devices synchronizes all filters. 8 to 5 flen [3:0] filter length bits. these bits must be set wh en the dl_filt bit is set before a user-defined filter is downlo aded. 4 byp f3 bypass filter 3. if this bit is 0, fi lter 3 (programmable fir) is bypassed. 3 byp f1 bypass filter 1. if this bit is 0, filter 1 is bypassed. th is should only occur when the user requires unfiltered modulator data to be output. 2 to 0 dec [2:0] decimation rate. these bits set the decimation rate of filter 2. all 0s implies that the filter is bypassed. a value of 1 corresponds to 2 decimation, a value of 2 correspon ds to 4 decimation, and so on, up to the maximum value of 5, corresponding to 32 decimation. 1 bit 15 to bit 9 are self-clearing bits. 2 only one of the bits from bit 14 to bit 11 can be set in any write operation because it determines the contents of the next re ad operation. control register 2address 0x0002 default value after reset : 0x009b recommended register setting for power-up and normal operation using clock divide-by-2 ( cdiv = 0) mode: 0x0002 msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 cdiv 0 pd lpwr 1 d1pd table 16. bit descriptions of control register 2 bit mnemonic description 5 cdiv clock divider bit. this sets the divide ratio of th e mclk signal to produce the internal iclk. setting cdiv = 0 divides the mclk by 2. if cdiv = 1, the iclk frequency is equal to the mclk. 3 pd power down. setting this bit powers down th e ad7760, reducing the power consumption to 6.35 mw. 2 lpwr low power. if this bit is set, the ad7760 is operating in a low power mode. the power consumption is reduced for a 6 db reduction in noise performance. 1 1 write 1 to this bit. 0 d1pd differential amplifier power down. setting this bit powers down the on-chip differential amplifier.
ad7760 rev. a | page 34 of 36 status register (read only) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 part 1 part 0 die 2 die 1 die 0 0 lpwr ovr dl_ok filtok ufilt byp f3 byp f1 dec2 dec1 dec0 table 17. bit descriptions of status register bit mnemonic comment 15, 14 part [1:0] part number. these bits are constant for the ad7760. 13 to 11 die [2:0] die number. these bits reflect the current ad 7760 die number for identification purposes within a system. 10 0 this bit is set to 0. 9 lpwr low power. if the ad7760 is operating in low power mode, this bit is set to 1. 8 ovr if the current analog input exceeds the cu rrent overrange threshol d, this bit is set. 7 dl_ok when downloading a user filter to th e ad7760, a checksum is generated. this checksum is compared to the one downloaded following the coefficients. if these checksums agree, this bit is set. 6 filtok when a user-defined filter is in use, a checksum is genera ted when the filter coefficients pass through the filter. this generated checksum is compared to the one downloaded. if they match, this bit is set. 5 ufilt if a user-defined filter is in use, this bit is set. 4 byp f3 bypass filter 3. if filter 3 is bypassed by setting the relevant bit in control register 1, this bit is also set. 3 byp f1 bypass filter 1. if filter 1 is bypassed by setting the relevant bit in control register 1, this bit is also set. 2 to 0 dec [2:0] decimation rate. these bits corr espond to the bits set in control register 1. offset registeraddress 0x0003 non-bit-mapped, default value 0x0000 the offset register uses twos complement notation and is scaled such that 0x7fff (maximum positive value) and 0x8000 (max- imum negative value) correspond to an offset of +0.78125% and ?0.78125%, respectively. offset correction is applied after any gain correction. using the default gain value of 1.25 and assuming a reference voltage of 4.096 v, the offset correction range is approximately 25 mv. gain registeraddress 0x0004 non-bit-mapped, default value 0xa000 the gain register is scaled such that 0x8000 corresponds to a gain of 1.0. the default value of this register is 1.25 (0xa000). this results in a full-scale digital output when the input is at 80% of v ref , tying in with the maximum analog input range of 80% of v ref p-p. overrange registeraddress 0x0005 non-bit-mapped, default value 0xcccc the overrange register value is compared with the output of the first decimation filter to obtain an overload indication with minimum propagation delay. this is prior to any gain scaling or offset adjustment. the default value is 0xcccc, which corresponds to 80% of v ref (the maximum permitted analog input voltage). assuming v ref = 4.096 v, the bit is then set when the input voltage exceeds approximately 6.55 v p-p differential. once the overrange bit is set, the dvalid bit in the status bits of the ad7760 ouptut is set to zero, providing another indication that an input overrange has occurred. note that the overrange bit is set immediately if the analog input voltage exceeds 100% of v ref for more than four consecutive samples at the modulator rate.
ad7760 rev. a | page 35 of 36 outline dimensions compliant to jedec standards ms-026-acd-hd 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 49 64 1 17 16 32 33 48 1.20 max 0.75 0.60 0.45 view a top view (pins down) pin 1 49 64 17 1 16 32 33 48 0.50 bsc lead pitch 0.38 0.32 0.22 bottom view (pins up) 6.00 bsc sq exposed pad 12.20 12.00 sq 11.80 10.20 10.00 sq 9.80 figure 59. 64-lead thin quad flat package, exposed pad [tqfp_ep] (sv-64-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad7760bsvz 1 ?40c to +85c 64-lead thin quad flat package, exposed pad [tqfp_ep] sv-64-2 ad7760bsvz-reel 1 ?40c to +85c 64-lead thin quad flat package, exposed pad [tqfp_ep] sv-64-2 eval-ad7760eb evaluation board 1 z = pb-free part.
ad7760 rev. a | page 36 of 36 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04975-0-8/06(a)

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